1. Field of the Invention
The present invention relates to a voltage-controlled oscillator (VCO) suitable for use in a monolithic CMOS phase lock loop that generates an even number of equally spaced phases for use with other circuitry.
2. Background Art
Most modern VLSI components have a phase lock loop (PLL) to multiply-up an external clock reference to a frequency that is used to clock the inside of the part. A component of the PLL is a voltage-controlled oscillator (VCO) that takes, as an input, an analog voltage that determines its output frequency. Thus, the VCO is a free running oscillator that is put in a feedback loop to control its operating frequency. Typically, the PLL is a multiplying PLL so that a low frequency external reference clock is multiplied up to some higher frequency. For example, a 200 MHz external reference clock is multiplied up to a range of 1.6 to 2.4 GHz.
A convention ring oscillator is typically employed as a VCO for CMOS technology. The conventional ring oscillator consists of a string of inverters having their supply controlled by a control voltage. The conventional ring oscillator requires an odd number of inverters that provides an odd number of phases.
If a VCO is used in a circuit to control the phase of an output signal digitally, an even number of phases is preferred that are equi-distance spaced along the period of oscillation. Since the conventional ring oscillator provides an odd number of phases, it is not suited to control the phase of an output signal digitally.
Differential ring oscillators have been built, suffer from small voltage swings and thus require level conversion and have frequency range limitations.